BibTeX records: Seng-Pan U

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@article{DBLP:journals/jssc/ChanZLZHWUM17,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Cheng Li and
               Wai{-}Hong Zhang and
               Iok{-}Meng Ho and
               Lai Wei and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {60-dB {SNDR} 100-MS/s {SAR} ADCs With Threshold Reconfigurable Reference
               Error Calibration},
  journal   = {J. Solid-State Circuits},
  volume    = {52},
  number    = {10},
  pages     = {2576--2588},
  year      = {2017},
  url       = {https://doi.org/10.1109/JSSC.2017.2728784},
  doi       = {10.1109/JSSC.2017.2728784},
  timestamp = {Thu, 19 Oct 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/ChanZLZHWUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/mj/LuoLHJSUM17,
  author    = {Ziyang Luo and
               Yan Lu and
               Mo Huang and
               Junmin Jiang and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A sub-1V 78-nA bandgap reference with curvature compensation},
  journal   = {Microelectronics Journal},
  volume    = {63},
  pages     = {35--40},
  year      = {2017},
  url       = {https://doi.org/10.1016/j.mejo.2017.02.016},
  doi       = {10.1016/j.mejo.2017.02.016},
  timestamp = {Mon, 29 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/mj/LuoLHJSUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/ChanZSMUM17,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Sai{-}Weng Sin and
               Boris Murmann and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Metastablility in {SAR} ADCs},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {64-II},
  number    = {2},
  pages     = {111--115},
  year      = {2017},
  url       = {https://doi.org/10.1109/TCSII.2016.2554798},
  doi       = {10.1109/TCSII.2016.2554798},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/ChanZSMUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/LuDHLSUM17,
  author    = {Yan Lu and
               Haojuan Dai and
               Mo Huang and
               Man{-}Kay Law and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A Wide Input Range Dual-Path {CMOS} Rectifier for {RF} Energy Harvesting},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {64-II},
  number    = {2},
  pages     = {166--170},
  year      = {2017},
  url       = {https://doi.org/10.1109/TCSII.2016.2554778},
  doi       = {10.1109/TCSII.2016.2554778},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/LuDHLSUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/ZhongZCSUM17,
  author    = {Jianyu Zhong and
               Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 12b 180MS/s 0.068mm\({}^{\mbox{2}}\) With Full-Calibration-Integrated
               Pipelined-SAR {ADC}},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {64},
  number    = {7},
  pages     = {1684--1695},
  year      = {2017},
  url       = {https://doi.org/10.1109/TCSI.2017.2679748},
  doi       = {10.1109/TCSI.2017.2679748},
  timestamp = {Wed, 26 Jul 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/ZhongZCSUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/ChanZSUMM17,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash {ADC}},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {64},
  number    = {8},
  pages     = {1966--1976},
  year      = {2017},
  url       = {https://doi.org/10.1109/TCSI.2017.2682268},
  doi       = {10.1109/TCSI.2017.2682268},
  timestamp = {Thu, 19 Oct 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/ChanZSUMM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/QiSUMM17,
  author    = {Liang Qi and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Franco Maloberti and
               Rui Paulo Martins},
  title     = {A 4.2-mW 77.1-dB {SNDR} 5-MHz {BW} {DT} 2-1 {MASH} {\(\Delta\)} {\(\Sigma\)}
               Modulator With Multirate Opamp Sharing},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {64-I},
  number    = {10},
  pages     = {2641--2654},
  year      = {2017},
  url       = {https://doi.org/10.1109/TCSI.2017.2693921},
  doi       = {10.1109/TCSI.2017.2693921},
  timestamp = {Wed, 11 Oct 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/QiSUMM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tvlsi/0001CUM17,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 10-bit 500-MS/s Partial-Interleaving Pipelined {SAR} {ADC} With
               Offset and Reference Mismatch Calibrations},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {25},
  number    = {1},
  pages     = {354--363},
  year      = {2017},
  url       = {https://doi.org/10.1109/TVLSI.2016.2576468},
  doi       = {10.1109/TVLSI.2016.2576468},
  timestamp = {Thu, 27 Jul 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tvlsi/0001CUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tvlsi/HussainSCUMM17,
  author    = {Arshad Hussain and
               Sai{-}Weng Sin and
               Chi{-}Hang Chan and
               Ben Seng{-}Pan U and
               Franco Maloberti and
               Rui Paulo Martins},
  title     = {Active-Passive {\(\Delta\)}{\(\Sigma\)} Modulator for High-Resolution
               and Low-Power Applications},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {25},
  number    = {1},
  pages     = {364--374},
  year      = {2017},
  url       = {https://doi.org/10.1109/TVLSI.2016.2580712},
  doi       = {10.1109/TVLSI.2016.2580712},
  timestamp = {Thu, 27 Jul 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tvlsi/HussainSCUMM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tvlsi/XingZCSYRUM17,
  author    = {Dezhi Xing and
               Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Fan Ye and
               Junyan Ren and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Seven-bit 700-MS/s Four-Way Time-Interleaved {SAR} {ADC} With Partial
               {\textdollar}V{\_}\{{\textbackslash}mathrm \{cm\}\}{\textdollar} -Based
               Switching},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {25},
  number    = {3},
  pages     = {1168--1172},
  year      = {2017},
  url       = {https://doi.org/10.1109/TVLSI.2016.2610864},
  doi       = {10.1109/TVLSI.2016.2610864},
  timestamp = {Mon, 27 Nov 2017 00:00:00 +0100},
  biburl    = {http://dblp.org/rec/bib/journals/tvlsi/XingZCSYRUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/Wang0CUM17,
  author    = {Guan{-}Cheng Wang and
               Yan Zhu and
               Chi{-}Hang Chan and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A missing-code-detection gain error calibration achieving 63dB {SNR}
               for an 11-bit {ADC}},
  booktitle = {43rd {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2017,
               Leuven, Belgium, September 11-14, 2017},
  pages     = {239--242},
  year      = {2017},
  crossref  = {DBLP:conf/esscirc/2017},
  url       = {https://doi.org/10.1109/ESSCIRC.2017.8094570},
  doi       = {10.1109/ESSCIRC.2017.8094570},
  timestamp = {Tue, 14 Nov 2017 10:17:15 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/Wang0CUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Chan0HZUM17,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Iok{-}Meng Ho and
               Wai{-}Hong Zhang and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {16.4 {A} 5mW 7b 2.4GS/s 1-then-2b/cycle {SAR} {ADC} with background
               offset calibration},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {282--283},
  year      = {2017},
  crossref  = {DBLP:conf/isscc/2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870371},
  doi       = {10.1109/ISSCC.2017.7870371},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/Chan0HZUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HuangLUM17,
  author    = {Mo Huang and
               Yan Lu and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {20.4 An output-capacitor-free analog-assisted digital low-dropout
               regulator with tri-loop control},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {342--343},
  year      = {2017},
  crossref  = {DBLP:conf/isscc/2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870401},
  doi       = {10.1109/ISSCC.2017.7870401},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/HuangLUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/JiangLKUM17,
  author    = {Junmin Jiang and
               Yan Lu and
               Wing{-}Hung Ki and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {20.5 {A} dual-symmetrical-output switched-capacitor converter with
               dynamic power cells and minimized cross regulation for application
               processors in 28nm {CMOS}},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {344--345},
  year      = {2017},
  crossref  = {DBLP:conf/isscc/2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870402},
  doi       = {10.1109/ISSCC.2017.7870402},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/JiangLKUM17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HuangLUM17a,
  author    = {Mo Huang and
               Yan Lu and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {22.4 {A} reconfigurable bidirectional wireless power transceiver with
               maximum-current charging mode and 58.6{\%} battery-to-battery efficiency},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {376--377},
  year      = {2017},
  crossref  = {DBLP:conf/isscc/2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870418},
  doi       = {10.1109/ISSCC.2017.7870418},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/HuangLUM17a},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DorisRRS17,
  author    = {Kostas Doris and
               David Robertson and
               Seung{-}Tak Ryu and
               Seng{-}Pan U},
  title     = {{F6:} Pushing the performance limit in data converters organizers:
               Venkatesh Srinivasan, Texas Instruments, Dallas, {TX}},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {515--517},
  year      = {2017},
  crossref  = {DBLP:conf/isscc/2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870484},
  doi       = {10.1109/ISSCC.2017.7870484},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/DorisRRS17},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/jssc/Chan0SUM16,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 6 b 5 GS/s 4 Interleaved 3 b/Cycle {SAR} {ADC}},
  journal   = {J. Solid-State Circuits},
  volume    = {51},
  number    = {2},
  pages     = {365--377},
  year      = {2016},
  url       = {https://doi.org/10.1109/JSSC.2015.2493167},
  doi       = {10.1109/JSSC.2015.2493167},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/Chan0SUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/jssc/ZhuCUM16,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR
               {ADC} in 65 nm {CMOS}},
  journal   = {J. Solid-State Circuits},
  volume    = {51},
  number    = {5},
  pages     = {1223--1234},
  year      = {2016},
  url       = {https://doi.org/10.1109/JSSC.2016.2522762},
  doi       = {10.1109/JSSC.2016.2522762},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/ZhuCUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/HuangLSUM16,
  author    = {Mo Huang and
               Yan Lu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A Fully Integrated Digital {LDO} With Coarse-Fine-Tuning and Burst-Mode
               Operation},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {63-II},
  number    = {7},
  pages     = {683--687},
  year      = {2016},
  url       = {https://doi.org/10.1109/TCSII.2016.2530094},
  doi       = {10.1109/TCSII.2016.2530094},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/HuangLSUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/HuangLSUMK16,
  author    = {Mo Huang and
               Yan Lu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins and
               Wing{-}Hung Ki},
  title     = {Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {63-II},
  number    = {9},
  pages     = {903--907},
  year      = {2016},
  url       = {https://doi.org/10.1109/TCSII.2016.2534778},
  doi       = {10.1109/TCSII.2016.2534778},
  timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/HuangLSUMK16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tvlsi/0001CWUM16,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               Si{-}Seng Wong and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit
               120 MS/s {SAR} {ADC}},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {24},
  number    = {3},
  pages     = {1203--1207},
  year      = {2016},
  url       = {https://doi.org/10.1109/TVLSI.2015.2442258},
  doi       = {10.1109/TVLSI.2015.2442258},
  timestamp = {Thu, 18 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tvlsi/0001CWUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tvlsi/Liu0CSUM16,
  author    = {Jianwei Liu and
               Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo da Silva Martins},
  title     = {Uniform Quantization Theory-Based Linearity Calibration for Split
               Capacitive {DAC} in an {SAR} {ADC}},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {24},
  number    = {7},
  pages     = {2603--2607},
  year      = {2016},
  url       = {https://doi.org/10.1109/TVLSI.2015.2509164},
  doi       = {10.1109/TVLSI.2015.2509164},
  timestamp = {Thu, 18 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tvlsi/Liu0CSUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HuangLUM16,
  author    = {Mo Huang and
               Yan Lu and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A digital {LDO} with transient enhancement and limit cycle oscillation
               reduction},
  booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
               2016, Jeju, South Korea, October 25-28, 2016},
  pages     = {25--28},
  year      = {2016},
  crossref  = {DBLP:conf/apccas/2016},
  url       = {https://doi.org/10.1109/APCCAS.2016.7803886},
  doi       = {10.1109/APCCAS.2016.7803886},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/HuangLUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/asscc/RenSLWUM16,
  author    = {Yuan Ren and
               Sai{-}Weng Sin and
               Chi{-}Seng Lam and
               Man{-}Chung Wong and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A high {DR} multi-channel stage-shared hybrid front-end for integrated
               power electronics controller},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  pages     = {57--60},
  year      = {2016},
  crossref  = {DBLP:conf/asscc/2016},
  url       = {https://doi.org/10.1109/ASSCC.2016.7844134},
  doi       = {10.1109/ASSCC.2016.7844134},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/RenSLWUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/asscc/QiuTZSZU16,
  author    = {Lei Qiu and
               Kai Tang and
               Yan Zhu and
               Liter Siek and
               Yuanjin Zheng and
               Seng{-}Pan U},
  title     = {A 10-bit 1GS/s 4-way {TI} {SAR} {ADC} with tap-interpolated {FIR}
               filter based time skew calibration},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  pages     = {77--80},
  year      = {2016},
  crossref  = {DBLP:conf/asscc/2016},
  url       = {https://doi.org/10.1109/ASSCC.2016.7844139},
  doi       = {10.1109/ASSCC.2016.7844139},
  timestamp = {Wed, 28 Jun 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/QiuTZSZU16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/asscc/Chan0HZLUM16,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Iok{-}Meng Ho and
               Wai{-}Hong Zhang and
               Chon{-}Lam Lio and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 0.011mm\({}^{\mbox{2}}\) 60dB {SNDR} 100MS/s reference error calibrated
               {SAR} {ADC} with 3pF decoupling capacitance for reference voltages},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  pages     = {145--148},
  year      = {2016},
  crossref  = {DBLP:conf/asscc/2016},
  url       = {https://doi.org/10.1109/ASSCC.2016.7844156},
  doi       = {10.1109/ASSCC.2016.7844156},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/Chan0HZLUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/Zhong0CSUM16,
  author    = {Jianyu Zhong and
               Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 12b 180MS/s 0.068mm\({}^{\mbox{2}}\) pipelined-SAR {ADC} with merged-residue
               {DAC} for noise reduction},
  booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
               Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
  pages     = {169--172},
  year      = {2016},
  crossref  = {DBLP:conf/esscirc/2016},
  url       = {https://doi.org/10.1109/ESSCIRC.2016.7598269},
  doi       = {10.1109/ESSCIRC.2016.7598269},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/Zhong0CSUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isicir/LiSUM16,
  author    = {Wei Li and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation
               applications},
  booktitle = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
               December 12-14, 2016},
  pages     = {1--4},
  year      = {2016},
  crossref  = {DBLP:conf/isicir/2016},
  url       = {https://doi.org/10.1109/ISICIR.2016.7829723},
  doi       = {10.1109/ISICIR.2016.7829723},
  timestamp = {Fri, 19 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isicir/LiSUM16},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/Zhong0SUM15,
  author    = {Jianyu Zhong and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Thermal and Reference Noise Analysis of Time-Interleaving {SAR} and
               Partial-Interleaving Pipelined-SAR ADCs},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {62},
  number    = {9},
  pages     = {2196--2206},
  year      = {2015},
  url       = {https://doi.org/10.1109/TCSI.2015.2452331},
  doi       = {10.1109/TCSI.2015.2452331},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/Zhong0SUM15},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LiuCSUM15,
  author    = {Jianwei Liu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 89fJ-FOM 6-bit 3.4GS/s flash {ADC} with 4x time-domain interpolation},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2015, Xia'men,
               China, November 9-11, 2015},
  pages     = {1--4},
  year      = {2015},
  crossref  = {DBLP:conf/asscc/2015},
  url       = {https://doi.org/10.1109/ASSCC.2015.7387463},
  doi       = {10.1109/ASSCC.2015.7387463},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/LiuCSUM15},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Chan0SUM15,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {26.5 {A} 5.5mW 6b 5GS/S 4{\texttimes}-lnterleaved 3b/cycle {SAR} {ADC}
               in 65nm {CMOS}},
  booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  pages     = {1--3},
  year      = {2015},
  crossref  = {DBLP:conf/isscc/2015},
  url       = {https://doi.org/10.1109/ISSCC.2015.7063128},
  doi       = {10.1109/ISSCC.2015.7063128},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/Chan0SUM15},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LuJKYSUM15,
  author    = {Yan Lu and
               Junmin Jiang and
               Wing{-}Hung Ki and
               C. Patrick Yue and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {20.4 {A} 123-phase {DC-DC} converter-ring with fast-DVS for microprocessors},
  booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  pages     = {1--3},
  year      = {2015},
  crossref  = {DBLP:conf/isscc/2015},
  url       = {https://doi.org/10.1109/ISSCC.2015.7063077},
  doi       = {10.1109/ISSCC.2015.7063077},
  timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/LuJKYSUM15},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuCCSUMM14,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               U. Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {Split-SAR ADCs: Improved Linearity With Power and Speed Optimization},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {22},
  number    = {2},
  pages     = {372--383},
  year      = {2014},
  url       = {https://doi.org/10.1109/TVLSI.2013.2242501},
  doi       = {10.1109/TVLSI.2013.2242501},
  timestamp = {Thu, 18 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tvlsi/ZhuCCSUMM14},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/0001CUM14,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR {ADC}},
  booktitle = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
               Lido, Italy, September 22-26, 2014},
  pages     = {211--214},
  year      = {2014},
  crossref  = {DBLP:conf/esscirc/2014},
  url       = {https://doi.org/10.1109/ESSCIRC.2014.6942059},
  doi       = {10.1109/ESSCIRC.2014.6942059},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/0001CUM14},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FengMSUM14,
  author    = {Da Feng and
               Franco Maloberti and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Jitter-resistant Capacitor Based Sine-Shaped {DAC} for Continuous-Time
               Sigma-Delta modulators},
  booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
               Melbourne, Victoria, Australia, June 1-5, 2014},
  pages     = {1348--1351},
  year      = {2014},
  crossref  = {DBLP:conf/iscas/2014},
  url       = {https://doi.org/10.1109/ISCAS.2014.6865393},
  doi       = {10.1109/ISCAS.2014.6865393},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/FengMSUM14},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/jssc/WongCZSUM13,
  author    = {Si{-}Seng Wong and
               U{-}Fat Chio and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved
               {SAR} {ADC}},
  journal   = {J. Solid-State Circuits},
  volume    = {48},
  number    = {8},
  pages     = {1783--1794},
  year      = {2013},
  url       = {https://doi.org/10.1109/JSSC.2013.2258832},
  doi       = {10.1109/JSSC.2013.2258832},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/WongCZSUM13},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/jssc/ChanZSUMM13,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash {ADC} in 65-nm {CMOS}},
  journal   = {J. Solid-State Circuits},
  volume    = {48},
  number    = {9},
  pages     = {2154--2169},
  year      = {2013},
  url       = {https://doi.org/10.1109/JSSC.2013.2264617},
  doi       = {10.1109/JSSC.2013.2264617},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/ChanZSUMM13},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DuHJSUM13,
  author    = {Yun Du and
               Tao He and
               Yang Jiang and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A continuous-time VCO-assisted VCO-based {\(\Sigma\)}{\(\Delta\)}
               modulator with 76.6dB {SNDR} and 10MHz {BW}},
  booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
               Beijing, China, May 19-23, 2013},
  pages     = {373--376},
  year      = {2013},
  crossref  = {DBLP:conf/iscas/2013},
  url       = {https://doi.org/10.1109/ISCAS.2013.6571858},
  doi       = {10.1109/ISCAS.2013.6571858},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/DuHJSUM13},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WuZDCCSUM13,
  author    = {Wen{-}Lan Wu and
               Yan Zhu and
               Li Ding and
               Chi{-}Hang Chan and
               U. Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A 0.6V 8b 100MS/s {SAR} {ADC} with minimized {DAC} capacitance and
               switching energy in 65nm {CMOS}},
  booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
               Beijing, China, May 19-23, 2013},
  pages     = {2239--2242},
  year      = {2013},
  crossref  = {DBLP:conf/iscas/2013},
  url       = {https://doi.org/10.1109/ISCAS.2013.6572322},
  doi       = {10.1109/ISCAS.2013.6572322},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/WuZDCCSUM13},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/jssc/ZhuCSUMM12,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {A 50-fJ 10-b 160-MS/s Pipelined-SAR {ADC} Decoupled Flip-Around {MDAC}
               and Self-Embedded Offset Cancellation},
  journal   = {J. Solid-State Circuits},
  volume    = {47},
  number    = {11},
  pages     = {2614--2626},
  year      = {2012},
  url       = {https://doi.org/10.1109/JSSC.2012.2211695},
  doi       = {10.1109/JSSC.2012.2211695},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/ZhuCSUMM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/jssc/WeiCCSUMM12,
  author    = {He Gong Wei and
               Chi{-}Hang Chan and
               U. Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {An 8-b 400-MS/s 2-b-Per-Cycle {SAR} {ADC} With Resistive {DAC}},
  journal   = {J. Solid-State Circuits},
  volume    = {47},
  number    = {11},
  pages     = {2763--2772},
  year      = {2012},
  url       = {https://doi.org/10.1109/JSSC.2012.2214181},
  doi       = {10.1109/JSSC.2012.2214181},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/WeiCCSUMM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/DuHJSUM12,
  author    = {Yun Du and
               Tao He and
               Yang Jiang and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A robust {NTF} zero optimization technique for both low and high OSRs
               sigma-delta modulators},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
               Kaohsiung, Taiwan, December 2-5, 2012},
  pages     = {29--32},
  year      = {2012},
  crossref  = {DBLP:conf/apccas/2012},
  url       = {https://doi.org/10.1109/APCCAS.2012.6418963},
  doi       = {10.1109/APCCAS.2012.6418963},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/DuHJSUM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HeDJSUM12,
  author    = {Tao He and
               Yun Du and
               Yang Jiang and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A {DT} 0-2 {MASH} {\(\Sigma\)}{\(\Delta\)} modulator with VCO-based
               quantizer for enhanced linearity},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
               Kaohsiung, Taiwan, December 2-5, 2012},
  pages     = {33--36},
  year      = {2012},
  crossref  = {DBLP:conf/apccas/2012},
  url       = {https://doi.org/10.1109/APCCAS.2012.6418964},
  doi       = {10.1109/APCCAS.2012.6418964},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/HeDJSUM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WuSUM12,
  author    = {Wen{-}Lan Wu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 10-bit {SAR} {ADC} with two redundant decisions and splitted-MSB-cap
               {DAC} array},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
               Kaohsiung, Taiwan, December 2-5, 2012},
  pages     = {268--271},
  year      = {2012},
  crossref  = {DBLP:conf/apccas/2012},
  url       = {https://doi.org/10.1109/APCCAS.2012.6419023},
  doi       = {10.1109/APCCAS.2012.6419023},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/WuSUM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/cicc/WongCZSUM12,
  author    = {Si{-}Seng Wong and
               U{-}Fat Chio and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved
               {SAR} {ADC}},
  booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
               {CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
  pages     = {1--4},
  year      = {2012},
  crossref  = {DBLP:conf/cicc/2012},
  url       = {https://doi.org/10.1109/CICC.2012.6330695},
  doi       = {10.1109/CICC.2012.6330695},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/cicc/WongCZSUM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/WangCSUWM12,
  author    = {Rui Wang and
               U{-}Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Zhihua Wang and
               Rui Paulo Martins},
  title     = {A 12-bit 110MS/s 4-stage single-opamp pipelined {SAR} {ADC} with ratio-based
               {GEC} technique},
  booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
               2012, Bordeaux, France, September 17-21, 2012},
  pages     = {265--268},
  year      = {2012},
  crossref  = {DBLP:conf/esscirc/2012},
  url       = {https://doi.org/10.1109/ESSCIRC.2012.6341336},
  doi       = {10.1109/ESSCIRC.2012.6341336},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/WangCSUWM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/YinWCSUWM12,
  author    = {Guohe Yin and
               He Gong Wei and
               U{-}Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Zhihua Wang and
               Rui Paulo Martins},
  title     = {A 0.024 mm\({}^{\mbox{2}}\) 4.9 fJ 10-bit 2 MS/s {SAR} {ADC} in 65
               nm {CMOS}},
  booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
               2012, Bordeaux, France, September 17-21, 2012},
  pages     = {377--380},
  year      = {2012},
  crossref  = {DBLP:conf/esscirc/2012},
  url       = {https://doi.org/10.1109/ESSCIRC.2012.6341364},
  doi       = {10.1109/ESSCIRC.2012.6341364},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/YinWCSUWM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HeJDSUM12,
  author    = {Tao He and
               Yang Jiang and
               Yun Du and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A 10MHz {BW} 78dB {DR} {CT} {\(\Sigma\)}{\(\Delta\)} modulator with
               novel switched high linearity VCO-based quantizer},
  booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
               2012, Seoul, Korea (South), May 20-23, 2012},
  pages     = {65--68},
  year      = {2012},
  crossref  = {DBLP:conf/iscas/2012},
  url       = {https://doi.org/10.1109/ISCAS.2012.6272116},
  doi       = {10.1109/ISCAS.2012.6272116},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/HeJDSUM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Chan0SUM12,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 3.8mW 8b 1GS/s 2b/cycle interleaving {SAR} {ADC} with compact {DAC}
               structure},
  booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
               13-15, 2012},
  pages     = {86--87},
  year      = {2012},
  crossref  = {DBLP:conf/vlsic/2012},
  url       = {https://doi.org/10.1109/VLSIC.2012.6243802},
  doi       = {10.1109/VLSIC.2012.6243802},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/vlsic/Chan0SUM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/0001CSUM12,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 34fJ 10b 500 MS/s partial-interleaving pipelined {SAR} {ADC}},
  booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
               13-15, 2012},
  pages     = {90--91},
  year      = {2012},
  crossref  = {DBLP:conf/vlsic/2012},
  url       = {https://doi.org/10.1109/VLSIC.2012.6243804},
  doi       = {10.1109/VLSIC.2012.6243804},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/vlsic/0001CSUM12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/asscc/0001CSUMM11,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {A 35 fJ 10b 160 MS/s pipelined-SAR {ADC} with decoupled flip-around
               {MDAC} and self-embedded offset cancellation},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
               South Korea, November 14-16, 2011},
  pages     = {61--64},
  year      = {2011},
  crossref  = {DBLP:conf/asscc/2011},
  url       = {https://doi.org/10.1109/ASSCC.2011.6123604},
  doi       = {10.1109/ASSCC.2011.6123604},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/0001CSUMM11},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/asscc/WongCCCSUM11,
  author    = {Si{-}Seng Wong and
               U. Fat Chio and
               Chi{-}Hang Chan and
               Hou{-}Lon Choi and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 4.8-bit {ENOB} 5-bit 500MS/s binary-search {ADC} with minimized
               number of comparators},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
               South Korea, November 14-16, 2011},
  pages     = {73--76},
  year      = {2011},
  crossref  = {DBLP:conf/asscc/2011},
  url       = {https://doi.org/10.1109/ASSCC.2011.6123607},
  doi       = {10.1109/ASSCC.2011.6123607},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/WongCCCSUM11},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/asscc/Chan0CSUM11,
  author    = {Chi{-}Hang Chan and
               Yan Zhu and
               U. Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A reconfigurable low-noise dynamic comparator with offset calibration
               in 90nm {CMOS}},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
               South Korea, November 14-16, 2011},
  pages     = {233--236},
  year      = {2011},
  crossref  = {DBLP:conf/asscc/2011},
  url       = {https://doi.org/10.1109/ASSCC.2011.6123645},
  doi       = {10.1109/ASSCC.2011.6123645},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/Chan0CSUM11},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/ChioCCSUM11,
  author    = {U. Fat Chio and
               Chi{-}Hang Chan and
               Hou{-}Lon Choi and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A 7-bit 300-MS/s subranging {ADC} with embedded threshold {\&}
               gain-loss calibration},
  booktitle = {Proceedings of the 37th European Solid-State Circuits Conference,
               {ESSCIRC} 2011, Helsinki, Finland, Sept. 12-16, 2011},
  pages     = {363--366},
  year      = {2011},
  crossref  = {DBLP:conf/esscirc/2011},
  url       = {https://doi.org/10.1109/ESSCIRC.2011.6044982},
  doi       = {10.1109/ESSCIRC.2011.6044982},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/ChioCCSUM11},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isocc/HussainSUM11,
  author    = {Arshad Hussain and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Hybrid loopfilter sigma-delta modulator with {NTF} zero compensation},
  booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
               November 17-18, 2011},
  pages     = {76--79},
  year      = {2011},
  crossref  = {DBLP:conf/isocc/2011},
  url       = {https://doi.org/10.1109/ISOCC.2011.6138650},
  doi       = {10.1109/ISOCC.2011.6138650},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isocc/HussainSUM11},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WeiCCSSMM11,
  author    = {He Gong Wei and
               Chi{-}Hang Chan and
               U{-}Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {A 0.024mm\({}^{\mbox{2}}\) 8b 400MS/s {SAR} {ADC} with 2b/cycle and
               resistive {DAC} in 65nm {CMOS}},
  booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
               Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
               2011},
  pages     = {188--190},
  year      = {2011},
  crossref  = {DBLP:conf/isscc/2011},
  url       = {https://doi.org/10.1109/ISSCC.2011.5746276},
  doi       = {10.1109/ISSCC.2011.5746276},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/WeiCCSSMM11},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/iet-cds/SinUM10,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital
               converter in 0.18 {\(\mu\)}m {CMOS} with minimised supply headroom},
  journal   = {{IET} Circuits, Devices {\&} Systems},
  volume    = {4},
  number    = {1},
  pages     = {1--13},
  year      = {2010},
  url       = {https://doi.org/10.1049/iet-cds.2008.0229},
  doi       = {10.1049/iet-cds.2008.0229},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/iet-cds/SinUM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/jssc/ZhuCCSUMM10,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               U. Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {A 10-bit 100-MS/s Reference-Free {SAR} {ADC} in 90 nm {CMOS}},
  journal   = {J. Solid-State Circuits},
  volume    = {45},
  number    = {6},
  pages     = {1111--1121},
  year      = {2010},
  url       = {https://doi.org/10.1109/JSSC.2010.2048498},
  doi       = {10.1109/JSSC.2010.2048498},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/jssc/ZhuCCSUMM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/WeiCZSUM10,
  author    = {He Gong Wei and
               U{-}Fat Chio and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm {CMOS}},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {57-II},
  number    = {1},
  pages     = {16--20},
  year      = {2010},
  url       = {https://doi.org/10.1109/TCSII.2009.2037260},
  doi       = {10.1109/TCSII.2009.2037260},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/WeiCZSUM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/ChioWZSUMM10,
  author    = {U{-}Fat Chio and
               He Gong Wei and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins and
               Franco Maloberti},
  title     = {Design and Experimental Verification of a Power Effective Flash-SAR
               Subranging {ADC}},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {57-II},
  number    = {8},
  pages     = {607--611},
  year      = {2010},
  url       = {https://doi.org/10.1109/TCSII.2010.2050937},
  doi       = {10.1109/TCSII.2010.2050937},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/ChioWZSUMM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/vlsi/ZhuCWSUM10,
  author    = {Yan Zhu and
               U. Fat Chio and
               He Gong Wei and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {Linearity Analysis on a Series-Split Capacitor Array for High-Speed
               {SAR} ADCs},
  journal   = {{VLSI} Design},
  volume    = {2010},
  pages     = {706548:1--706548:8},
  year      = {2010},
  url       = {https://doi.org/10.1155/2010/706548},
  doi       = {10.1155/2010/706548},
  timestamp = {Sat, 27 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/vlsi/ZhuCWSUM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/DingSUM10,
  author    = {Li Ding and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {An efficient {DAC} and interstage gain error calibration technique
               for multi-bit pipelined ADCs},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
               Kuala Lumpur, Malaysia, December 6-9, 2010},
  pages     = {208--211},
  year      = {2010},
  crossref  = {DBLP:conf/apccas/2010},
  url       = {https://doi.org/10.1109/APCCAS.2010.5774899},
  doi       = {10.1109/APCCAS.2010.5774899},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/DingSUM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/JiangWCSUM10,
  author    = {Yang Jiang and
               Kim{-}Fai Wong and
               Chen{-}Yan Cai and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A reduced jitter-sensitivity clock generation technique for continuous-time
               {\(\Sigma\)}{\(\Delta\)} modulators},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
               Kuala Lumpur, Malaysia, December 6-9, 2010},
  pages     = {1011--1014},
  year      = {2010},
  crossref  = {DBLP:conf/apccas/2010},
  url       = {https://doi.org/10.1109/APCCAS.2010.5774943},
  doi       = {10.1109/APCCAS.2010.5774943},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/JiangWCSUM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/JiangWCSUM10,
  author    = {Yang Jiang and
               Kim{-}Fai Wong and
               Chen{-}Yan Cai and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity
               in Continuous-Time sigma-delta modulators},
  booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
               Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
  pages     = {547--550},
  year      = {2010},
  crossref  = {DBLP:conf/icecsys/2010},
  url       = {https://doi.org/10.1109/ICECS.2010.5724570},
  doi       = {10.1109/ICECS.2010.5724570},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/JiangWCSUM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/YinCWSUMW10,
  author    = {Guohe Yin and
               U. Fat Chio and
               He Gong Wei and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins and
               Zhihua Wang},
  title     = {An ultra low power 9-bit 1-MS/s pipelined {SAR} {ADC} for bio-medical
               applications},
  booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
               Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
  pages     = {878--881},
  year      = {2010},
  crossref  = {DBLP:conf/icecsys/2010},
  url       = {https://doi.org/10.1109/ICECS.2010.5724652},
  doi       = {10.1109/ICECS.2010.5724652},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/YinCWSUMW10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhuCCSSM10,
  author    = {Yan Zhu and
               Chi{-}Hang Chan and
               U. Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A voltage feedback charge compensation technique for split {DAC} architecture
               in {SAR} ADCs},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
               30 - June 2, 2010, Paris, France},
  pages     = {4061--4064},
  year      = {2010},
  crossref  = {DBLP:conf/iscas/2010},
  url       = {https://doi.org/10.1109/ISCAS.2010.5537634},
  doi       = {10.1109/ISCAS.2010.5537634},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/ZhuCCSSM10},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/MakUM08,
  author    = {Pui{-}In Mak and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {On the Design of a Programmable-Gain Amplifier With Built-In Compact
               DC-Offset Cancellers for Very Low-Voltage {WLAN} Systems},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {55-I},
  number    = {2},
  pages     = {496--509},
  year      = {2008},
  url       = {https://doi.org/10.1109/TCSI.2007.910643},
  doi       = {10.1109/TCSI.2007.910643},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/MakUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/SinCUM08,
  author    = {Sai{-}Weng Sin and
               U{-}Fat Chio and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling
               Bandwidth Mismatch},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {55-II},
  number    = {7},
  pages     = {648--652},
  year      = {2008},
  url       = {https://doi.org/10.1109/TCSII.2008.921600},
  doi       = {10.1109/TCSII.2008.921600},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/SinCUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/SinUM08,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and
               Switched-Opamps},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {55-I},
  number    = {8},
  pages     = {2188--2201},
  year      = {2008},
  url       = {https://doi.org/10.1109/TCSI.2008.918171},
  doi       = {10.1109/TCSI.2008.918171},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/SinUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/DingCWSUM08,
  author    = {Li Ding and
               Sio Chan and
               Kim{-}Fai Wong and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo da Silva Martins},
  title     = {A pseudo-differential comparator-based pipelined {ADC} with common
               mode feedforward technique},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
               Macao, China, November 30 2008 - December 3, 2008},
  pages     = {276--279},
  year      = {2008},
  crossref  = {DBLP:conf/apccas/2008},
  url       = {https://doi.org/10.1109/APCCAS.2008.4746013},
  doi       = {10.1109/APCCAS.2008.4746013},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/DingCWSUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KongUM08,
  author    = {Ngai Kong and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A novel {CMOS} switched-current mode sequential shift forward inference
               circuit for fuzzy logic controller},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
               Macao, China, November 30 2008 - December 3, 2008},
  pages     = {396--399},
  year      = {2008},
  crossref  = {DBLP:conf/apccas/2008},
  url       = {https://doi.org/10.1109/APCCAS.2008.4746043},
  doi       = {10.1109/APCCAS.2008.4746043},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/KongUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WongLUM08,
  author    = {Kim{-}Fai Wong and
               Ka{-}Ian Lei and
               Seng{-}Pan U and
               Rui Paulo da Silva Martins},
  title     = {A 1-V 90dB {DR} audio stereo {DAC} with embedding headphone driver},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
               Macao, China, November 30 2008 - December 3, 2008},
  pages     = {1160--1163},
  year      = {2008},
  crossref  = {DBLP:conf/apccas/2008},
  url       = {https://doi.org/10.1109/APCCAS.2008.4746231},
  doi       = {10.1109/APCCAS.2008.4746231},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/WongLUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ChioWZSUM08,
  author    = {U. Fat Chio and
               He Gong Wei and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo da Silva Martins},
  title     = {A self-timing switch-driving register by precharge-evaluate logic
               for high-speed {SAR} ADCs},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
               Macao, China, November 30 2008 - December 3, 2008},
  pages     = {1164--1167},
  year      = {2008},
  crossref  = {DBLP:conf/apccas/2008},
  url       = {https://doi.org/10.1109/APCCAS.2008.4746232},
  doi       = {10.1109/APCCAS.2008.4746232},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/ChioWZSUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WeiCZSUM08,
  author    = {He Gong Wei and
               U. Fat Chio and
               Yan Zhu and
               Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo da Silva Martins},
  title     = {A process- and temperature- insensitive current-controlled delay generator
               for sampled-data systems},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
               Macao, China, November 30 2008 - December 3, 2008},
  pages     = {1192--1195},
  year      = {2008},
  crossref  = {DBLP:conf/apccas/2008},
  url       = {https://doi.org/10.1109/APCCAS.2008.4746239},
  doi       = {10.1109/APCCAS.2008.4746239},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/WeiCZSUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/0001CWSUM08,
  author    = {Yan Zhu and
               U. Fat Chio and
               He Gong Wei and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A power-efficient capacitor structure for high-speed charge recycling
               {SAR} ADCs},
  booktitle = {15th {IEEE} International Conference on Electronics, Circuits and
               Systems, {ICECS} 2008, St. Julien's, Malta, August 31 2008-September
               3, 2008},
  pages     = {642--645},
  year      = {2008},
  crossref  = {DBLP:conf/icecsys/2008},
  url       = {https://doi.org/10.1109/ICECS.2008.4674935},
  doi       = {10.1109/ICECS.2008.4674935},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/0001CWSUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WeiCSUM08,
  author    = {He Gong Wei and
               U. Fat Chio and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A power scalable 6-bit 1.2GS/s flash {ADC} with power on/off Track-and-Hold
               and preamplifier},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
               May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
  pages     = {5--8},
  year      = {2008},
  crossref  = {DBLP:conf/iscas/2008},
  url       = {https://doi.org/10.1109/ISCAS.2008.4541340},
  doi       = {10.1109/ISCAS.2008.4541340},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/WeiCSUM08},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/iet-cds/MakUM07,
  author    = {Pui{-}In Mak and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Experimental 1-V flexible-IF {CMOS} analoguebaseband chain for {IEEE}
               802.11a/b/g {WLAN} receivers},
  journal   = {{IET} Circuits, Devices {\&} Systems},
  volume    = {1},
  number    = {6},
  pages     = {415--426},
  year      = {2007},
  url       = {https://doi.org/10.1049/iet-cds:20070094},
  doi       = {10.1049/iet-cds:20070094},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/iet-cds/MakUM07},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MokMUM07,
  author    = {Weng{-}leng Mok and
               Pui{-}In Mak and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A Highly-Linear Successive-Approximation Front-End Digitizer with
               Built-in Sample-and-Hold Function for Pipeline/Two-Step {ADC}},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
               May 2007, New Orleans, Louisiana, {USA}},
  pages     = {1947--1950},
  year      = {2007},
  crossref  = {DBLP:conf/iscas/2007},
  url       = {https://doi.org/10.1109/ISCAS.2007.378357},
  doi       = {10.1109/ISCAS.2007.378357},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/MokMUM07},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/apccas/IeongUM06,
  author    = {Ka{-}Hou Ao Ieong and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A 1-V 2.5-mW Transient-Improved Current-Steering {DAC} using Charge-Removal-Replacement
               Technique},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
               2006, Singapore, 4-7 December 2006},
  pages     = {183--186},
  year      = {2006},
  crossref  = {DBLP:conf/apccas/2006},
  url       = {https://doi.org/10.1109/APCCAS.2006.342362},
  doi       = {10.1109/APCCAS.2006.342362},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/IeongUM06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChioUM06,
  author    = {Kin{-}Sang Chio and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A dual-mode low-distortion sigma-delta modulator with relaxing comparator
               accuracy},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
               May 2006, Island of Kos, Greece},
  year      = {2006},
  crossref  = {DBLP:conf/iscas/2006},
  url       = {https://doi.org/10.1109/ISCAS.2006.1692979},
  doi       = {10.1109/ISCAS.2006.1692979},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/ChioUM06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LaoUM06,
  author    = {Chon{-}In Lao and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling
               mismatch-free resonator},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
               May 2006, Island of Kos, Greece},
  year      = {2006},
  crossref  = {DBLP:conf/iscas/2006},
  url       = {https://doi.org/10.1109/ISCAS.2006.1692652},
  doi       = {10.1109/ISCAS.2006.1692652},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/LaoUM06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MaSUM06,
  author    = {Jun{-}Xia Ma and
               Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash
               {ADC} for {UWB} applications},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
               May 2006, Island of Kos, Greece},
  year      = {2006},
  crossref  = {DBLP:conf/iscas/2006},
  url       = {https://doi.org/10.1109/ISCAS.2006.1693581},
  doi       = {10.1109/ISCAS.2006.1693581},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/MaSUM06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakUM06,
  author    = {Pui{-}In Mak and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {Design and test strategy underlying a low-voltage analog-baseband
               {IC} for 802.11a/b/g {WLAN} SiP receivers},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
               May 2006, Island of Kos, Greece},
  year      = {2006},
  crossref  = {DBLP:conf/iscas/2006},
  url       = {https://doi.org/10.1109/ISCAS.2006.1693124},
  doi       = {10.1109/ISCAS.2006.1693124},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/MakUM06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM06,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A novel low-voltage finite-gain compensation technique for high-speed
               reset- and switched-opamp circuits},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
               May 2006, Island of Kos, Greece},
  year      = {2006},
  crossref  = {DBLP:conf/iscas/2006},
  url       = {https://doi.org/10.1109/ISCAS.2006.1693454},
  doi       = {10.1109/ISCAS.2006.1693454},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/SinUM06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tcas/MakUM05,
  author    = {Pui{-}In Mak and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Two-step channel selection-a novel technique for reconfigurable multistandard
               transceiver front-ends},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {52-I},
  number    = {7},
  pages     = {1302--1315},
  year      = {2005},
  url       = {https://doi.org/10.1109/TCSI.2005.851722},
  doi       = {10.1109/TCSI.2005.851722},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tcas/MakUM05},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/cicc/MakUM05,
  author    = {Pui{-}In Mak and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A 1-V transient-free and DC-offset-canceled {PGA} with a 17.1-MHz
               constant bandwidth over 52-dB control range in 0.35-/spl mu/m {CMOS}},
  booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
               {CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
               18-21, 2005},
  pages     = {649--652},
  year      = {2005},
  crossref  = {DBLP:conf/cicc/2005},
  url       = {https://doi.org/10.1109/CICC.2005.1568753},
  doi       = {10.1109/CICC.2005.1568753},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/cicc/MakUM05},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/IeongFMUM05,
  author    = {Ka{-}Hou Ao Ieong and
               Chong{-}Yin Fok and
               Pui{-}In Mak and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A frequency up-conversion and two-step channel selection embedded
               {CMOS} {D/A} interface},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
               May 2005, Kobe, Japan},
  pages     = {392--395},
  year      = {2005},
  crossref  = {DBLP:conf/iscas/2005},
  url       = {https://doi.org/10.1109/ISCAS.2005.1464607},
  doi       = {10.1109/ISCAS.2005.1464607},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/IeongFMUM05},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM05a,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A novel very low-voltage {SC-CMFB} technique for fully-differential
               reset-opamp circuits},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
               May 2005, Kobe, Japan},
  pages     = {1581--1584},
  year      = {2005},
  crossref  = {DBLP:conf/iscas/2005},
  url       = {https://doi.org/10.1109/ISCAS.2005.1464904},
  doi       = {10.1109/ISCAS.2005.1464904},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/SinUM05a},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM05,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A novel low-voltage cross-coupled passive sampling branch for reset-
               and switched-opamp circuits},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
               May 2005, Kobe, Japan},
  pages     = {1585--1588},
  year      = {2005},
  crossref  = {DBLP:conf/iscas/2005},
  url       = {https://doi.org/10.1109/ISCAS.2005.1464905},
  doi       = {10.1109/ISCAS.2005.1464905},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/SinUM05},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LaoUM05,
  author    = {Chon{-}In Lao and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
               May 2005, Kobe, Japan},
  pages     = {3095--3098},
  year      = {2005},
  crossref  = {DBLP:conf/iscas/2005},
  url       = {https://doi.org/10.1109/ISCAS.2005.1465282},
  doi       = {10.1109/ISCAS.2005.1465282},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/LaoUM05},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChioUM05,
  author    = {Kin{-}Sang Chio and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A robust 3rd order low-distortion multi-bit sigma-delta modulator
               with reduced number of op-amps for {WCDMA}},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
               May 2005, Kobe, Japan},
  pages     = {3099--3102},
  year      = {2005},
  crossref  = {DBLP:conf/iscas/2005},
  url       = {https://doi.org/10.1109/ISCAS.2005.1465283},
  doi       = {10.1109/ISCAS.2005.1465283},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/ChioUM05},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@article{DBLP:journals/tim/USM04,
  author    = {Seng{-}Pan U. and
               Sai{-}Weng Sin and
               Rui Paulo Martins},
  title     = {Exact spectra analysis of sampled signals with jitter-induced nonuniformly
               holding effects},
  journal   = {{IEEE} Trans. Instrumentation and Measurement},
  volume    = {53},
  number    = {4},
  pages     = {1279--1288},
  year      = {2004},
  url       = {https://doi.org/10.1109/TIM.2004.830787},
  doi       = {10.1109/TIM.2004.830787},
  timestamp = {Sat, 27 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/journals/tim/USM04},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinUM04,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A generalized timing-skew-free, multi-phase clock generation platform
               for parallel sampled-data systems},
  booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  pages     = {369--372},
  year      = {2004},
  crossref  = {DBLP:conf/iscas/2004},
  timestamp = {Fri, 20 May 2016 09:53:46 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/SinUM04},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakUM04,
  author    = {Pui{-}In Mak and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A low-IF/zero-IF reconfigurable receiver with two-step channel selection
               technique for multistandard applications},
  booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  pages     = {417--420},
  year      = {2004},
  crossref  = {DBLP:conf/iscas/2004},
  timestamp = {Fri, 20 May 2016 09:53:46 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/MakUM04},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakWU04,
  author    = {Pui{-}In Mak and
               Man{-}Chung Wong and
               Seng{-}Pan U.},
  title     = {A 3D {PWM} control, H-bridge tri-level inverter for power quality
               compensation in three-phase four-wired systems},
  booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  pages     = {948--951},
  year      = {2004},
  crossref  = {DBLP:conf/iscas/2004},
  timestamp = {Fri, 20 May 2016 09:53:46 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/MakWU04},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MakMMSHNSM04,
  author    = {Pui{-}In Mak and
               Kin{-}Kwan Ma and
               Weng{-}leng Mok and
               Chi{-}sam Sou and
               Kit{-}man Ho and
               Cheng{-}Man Ng and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {An I/Q-multiplexed and OTA-shared {CMOS} pipelined {ADC} with an {A-DQS}
               {S/H} front-end for two-step-channel-select low-IF receiver},
  booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  pages     = {1068--1071},
  year      = {2004},
  crossref  = {DBLP:conf/iscas/2004},
  timestamp = {Fri, 20 May 2016 09:53:46 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/MakMMSHNSM04},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/icassp/SinUM03,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held
               signals},
  booktitle = {2003 {IEEE} International Conference on Acoustics, Speech, and Signal
               Processing, {ICASSP} '03, Hong Kong, April 6-10, 2003},
  pages     = {253--256},
  year      = {2003},
  crossref  = {DBLP:conf/icassp/2003},
  url       = {https://doi.org/10.1109/ICASSP.2003.1201666},
  doi       = {10.1109/ICASSP.2003.1201666},
  timestamp = {Fri, 19 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icassp/SinUM03},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MakSUM03,
  author    = {Pui{-}In Mak and
               Chi{-}sam Sou and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {Frequency-downconversion and {IF} channel selection {A-DQS} sample-and-hold
               pair for two-step-channel-select low-IF receiver},
  booktitle = {Proceedings of the 2003 10th {IEEE} International Conference on Electronics,
               Circuits and Systems, {ICECS} 2003, Sharjah, United Arab Emirates,
               December 14-17, 2003},
  pages     = {479--482},
  year      = {2003},
  crossref  = {DBLP:conf/icecsys/2003},
  url       = {https://doi.org/10.1109/ICECS.2003.1301826},
  doi       = {10.1109/ICECS.2003.1301826},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/MakSUM03},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MakUM03,
  author    = {Pui{-}In Mak and
               Seng{-}Pan U and
               Rui Paulo Martins},
  title     = {A front-to-back-end modeling of {I/Q} mismatch effects in a complex-IF
               receiver for image-rejection enhancement},
  booktitle = {Proceedings of the 2003 10th {IEEE} International Conference on Electronics,
               Circuits and Systems, {ICECS} 2003, Sharjah, United Arab Emirates,
               December 14-17, 2003},
  pages     = {631--634},
  year      = {2003},
  crossref  = {DBLP:conf/icecsys/2003},
  url       = {https://doi.org/10.1109/ICECS.2003.1301864},
  doi       = {10.1109/ICECS.2003.1301864},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/MakUM03},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SinSMJF03,
  author    = {Sai{-}Weng Sin and
               Seng{-}Pan U. and
               Rui Paulo Martins and
               Jos{\'{e}} E. Franca},
  title     = {Timing-mismatch analysis in high-speed analog front-end with nonuniformly
               holding output},
  booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
               {ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
  pages     = {129--132},
  year      = {2003},
  crossref  = {DBLP:conf/iscas/2003},
  url       = {https://doi.org/10.1109/ISCAS.2003.1205517},
  doi       = {10.1109/ISCAS.2003.1205517},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/SinSMJF03},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LaoLAMUM03,
  author    = {Chon{-}In Lao and
               Ho{-}leng Leong and
               Kuoi{-}Fok Au and
               Kuok{-}Hang Mok and
               Seng{-}Pan U. and
               Rui Paulo Martins},
  title     = {A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp
               {SC} resonator with double-sampling},
  booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
               {ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
  pages     = {1061--1064},
  year      = {2003},
  crossref  = {DBLP:conf/iscas/2003},
  url       = {https://doi.org/10.1109/ISCAS.2003.1205750},
  doi       = {10.1109/ISCAS.2003.1205750},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/LaoLAMUM03},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF02,
  author    = {Seng{-}Pan U. and
               Rui Paulo Martins and
               Jos{\'{e}} E. Franca},
  title     = {Design and analysis of low timing-skew clock generation for time-interleaved
               sampled-data systems},
  booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
               {ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
  pages     = {441--444},
  year      = {2002},
  crossref  = {DBLP:conf/iscas/2002},
  url       = {https://doi.org/10.1109/ISCAS.2002.1010486},
  doi       = {10.1109/ISCAS.2002.1010486},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/UMF02},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF01,
  author    = {Seng{-}Pan U. and
               Rui Paulo Martins and
               Jos{\'{e}} E. Franca},
  title     = {High-frequency low-power multirate {SC} realizations for {NTSC/PAL}
               digital video filtering},
  booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
               {ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
  pages     = {204--207},
  year      = {2001},
  crossref  = {DBLP:conf/iscas/2001},
  url       = {https://doi.org/10.1109/ISCAS.2001.921826},
  doi       = {10.1109/ISCAS.2001.921826},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/UMF01},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF01a,
  author    = {Seng{-}Pan U. and
               Rui Paulo Martins and
               Jos{\'{e}} E. Franca},
  title     = {A high-speed frequency up-translated {SC} bandpass filter with auto-zeroing
               for {DDFS} systems},
  booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
               {ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
  pages     = {320--323},
  year      = {2001},
  crossref  = {DBLP:conf/iscas/2001},
  url       = {https://doi.org/10.1109/ISCAS.2001.921857},
  doi       = {10.1109/ISCAS.2001.921857},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/UMF01a},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF00,
  author    = {Seng{-}Pan U and
               Rui P. Martins and
               Jose E. Franca},
  title     = {A linear-phase halfband {SC} video interpolation filter with coefficient-sharing
               and spread-reduction},
  booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
               Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
               May 2000, Proceedings},
  pages     = {177--180},
  year      = {2000},
  crossref  = {DBLP:conf/iscas/2000},
  url       = {https://doi.org/10.1109/ISCAS.2000.856025},
  doi       = {10.1109/ISCAS.2000.856025},
  timestamp = {Sun, 22 Oct 2017 13:09:25 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/UMF00},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF99,
  author    = {Seng{-}Pan U. and
               Rui Paulo Martins and
               Jos{\'{e}} E. Franca},
  title     = {Highly accurate mismatch-free {SC} delay circuits with reduced finite
               gain and offset sensitivity},
  booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
               {ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
  pages     = {57--60},
  year      = {1999},
  crossref  = {DBLP:conf/iscas/1999},
  url       = {https://doi.org/10.1109/ISCAS.1999.780618},
  doi       = {10.1109/ISCAS.1999.780618},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/UMF99},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UMF99a,
  author    = {Seng{-}Pan U. and
               Rui Paulo Martins and
               Jos{\'{e}} E. Franca},
  title     = {High performance multirate {SC} circuits with predictive correlated
               double sampling technique},
  booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
               {ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
  pages     = {77--80},
  year      = {1999},
  crossref  = {DBLP:conf/iscas/1999},
  url       = {https://doi.org/10.1109/ISCAS.1999.780623},
  doi       = {10.1109/ISCAS.1999.780623},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/UMF99a},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/esscirc/2017,
  title     = {43rd {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2017,
               Leuven, Belgium, September 11-14, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8061155},
  isbn      = {978-1-5090-5025-3},
  timestamp = {Tue, 14 Nov 2017 10:17:15 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/2017},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/isscc/2017,
  title     = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7866667},
  isbn      = {978-1-5090-3758-2},
  timestamp = {Fri, 10 Mar 2017 11:00:31 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/2017},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/apccas/2016,
  title     = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
               2016, Jeju, South Korea, October 25-28, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7786273},
  isbn      = {978-1-5090-1570-2},
  timestamp = {Mon, 09 Jan 2017 13:48:09 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/2016},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/asscc/2016,
  title     = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7833314},
  isbn      = {978-1-5090-3699-8},
  timestamp = {Tue, 14 Mar 2017 15:43:11 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/2016},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/esscirc/2016,
  title     = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
               Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7585490},
  isbn      = {978-1-5090-2972-3},
  timestamp = {Tue, 25 Oct 2016 12:51:29 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/2016},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/isicir/2016,
  title     = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
               December 12-14, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7822827},
  isbn      = {978-1-4673-9019-4},
  timestamp = {Sun, 23 Apr 2017 15:45:39 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isicir/2016},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/asscc/2015,
  title     = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2015, Xia'men,
               China, November 9-11, 2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7378179},
  isbn      = {978-1-4673-7191-9},
  timestamp = {Wed, 23 Nov 2016 12:36:45 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/2015},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/isscc/2015,
  title     = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7054075},
  isbn      = {978-1-4799-6223-5},
  timestamp = {Tue, 24 Mar 2015 08:51:19 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/2015},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/esscirc/2014,
  title     = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
               Lido, Italy, September 22-26, 2014},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6932855},
  isbn      = {978-1-4799-5694-4},
  timestamp = {Fri, 09 Jan 2015 12:43:09 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/2014},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2014,
  title     = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
               Melbourne, Victoria, Australia, June 1-5, 2014},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6852006},
  isbn      = {978-1-4799-3431-7},
  timestamp = {Fri, 20 May 2016 09:19:46 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2014},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2013,
  title     = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
               Beijing, China, May 19-23, 2013},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6560459},
  isbn      = {978-1-4673-5760-9},
  timestamp = {Mon, 26 Aug 2013 07:33:58 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2013},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/apccas/2012,
  title     = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
               Kaohsiung, Taiwan, December 2-5, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6412846},
  isbn      = {978-1-4577-1728-4},
  timestamp = {Fri, 08 May 2015 15:30:14 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/2012},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/cicc/2012,
  title     = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
               {CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6320859},
  isbn      = {978-1-4673-1555-5},
  timestamp = {Tue, 23 Oct 2012 13:51:35 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/cicc/2012},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/esscirc/2012,
  title     = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
               2012, Bordeaux, France, September 17-21, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6331297},
  isbn      = {978-1-4673-2212-6},
  timestamp = {Thu, 15 Nov 2012 13:04:33 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/2012},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2012,
  title     = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
               2012, Seoul, Korea (South), May 20-23, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6257548},
  isbn      = {978-1-4673-0218-0},
  timestamp = {Mon, 08 Oct 2012 14:49:04 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2012},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/vlsic/2012,
  title     = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
               13-15, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6235082},
  isbn      = {978-1-4673-0848-9},
  timestamp = {Wed, 16 Mar 2016 12:11:17 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/vlsic/2012},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/asscc/2011,
  title     = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
               South Korea, November 14-16, 2011},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6118260},
  isbn      = {978-1-4577-1784-0},
  timestamp = {Wed, 29 Mar 2017 14:34:45 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/asscc/2011},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/esscirc/2011,
  title     = {Proceedings of the 37th European Solid-State Circuits Conference,
               {ESSCIRC} 2011, Helsinki, Finland, Sept. 12-16, 2011},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6034695},
  isbn      = {978-1-4577-0703-2},
  timestamp = {Mon, 31 Oct 2011 12:02:30 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/esscirc/2011},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/isocc/2011,
  title     = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
               November 17-18, 2011},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6126155},
  isbn      = {978-1-4577-0709-4},
  timestamp = {Thu, 16 Mar 2017 14:51:35 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/isocc/2011},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/isscc/2011,
  title     = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
               Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
               2011},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5740653},
  isbn      = {978-1-61284-303-2},
  timestamp = {Fri, 30 Sep 2011 11:17:51 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/isscc/2011},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/apccas/2010,
  title     = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
               Kuala Lumpur, Malaysia, December 6-9, 2010},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5767825},
  isbn      = {978-1-4244-7454-7},
  timestamp = {Thu, 06 Mar 2014 08:39:29 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/2010},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/icecsys/2010,
  title     = {17th {IEEE} International Conference on Electronics, Circuits, and
               Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5720492},
  isbn      = {978-1-4244-8155-2},
  timestamp = {Tue, 29 Nov 2011 15:56:51 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/2010},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2010,
  title     = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
               30 - June 2, 2010, Paris, France},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5512009},
  isbn      = {978-1-4244-5308-5},
  timestamp = {Fri, 20 May 2016 09:38:10 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2010},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/apccas/2008,
  title     = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
               Macao, China, November 30 2008 - December 3, 2008},
  publisher = {{IEEE}},
  year      = {2008},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4723905},
  isbn      = {978-1-4244-2342-2},
  timestamp = {Fri, 08 May 2015 15:30:14 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/2008},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/icecsys/2008,
  title     = {15th {IEEE} International Conference on Electronics, Circuits and
               Systems, {ICECS} 2008, St. Julien's, Malta, August 31 2008-September
               3, 2008},
  publisher = {{IEEE}},
  year      = {2008},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4664823},
  isbn      = {978-1-4244-2181-7},
  timestamp = {Tue, 22 Apr 2014 15:56:46 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/2008},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2008,
  title     = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
               May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
  publisher = {{IEEE}},
  year      = {2008},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4534149},
  isbn      = {978-1-4244-1683-7},
  timestamp = {Fri, 20 May 2016 09:40:26 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2008},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2007,
  title     = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
               May 2007, New Orleans, Louisiana, {USA}},
  publisher = {{IEEE}},
  year      = {2007},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4252534},
  isbn      = {1-4244-0920-9},
  timestamp = {Fri, 20 May 2016 09:41:11 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2007},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/apccas/2006,
  title     = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
               2006, Singapore, 4-7 December 2006},
  publisher = {{IEEE}},
  year      = {2006},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4145316},
  isbn      = {1-4244-0387-1},
  timestamp = {Fri, 08 May 2015 15:30:14 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/apccas/2006},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2006,
  title     = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
               May 2006, Island of Kos, Greece},
  publisher = {{IEEE}},
  year      = {2006},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11145},
  isbn      = {0-7803-9389-9},
  timestamp = {Fri, 20 May 2016 09:41:50 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2006},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/cicc/2005,
  title     = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
               {CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
               18-21, 2005},
  publisher = {{IEEE}},
  year      = {2005},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10489},
  isbn      = {0-7803-9023-7},
  timestamp = {Wed, 23 Dec 2015 10:42:35 +0100},
  biburl    = {http://dblp.org/rec/bib/conf/cicc/2005},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2005,
  title     = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
               May 2005, Kobe, Japan},
  publisher = {{IEEE}},
  year      = {2005},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9898},
  isbn      = {0-7803-8834-8},
  timestamp = {Fri, 20 May 2016 09:46:35 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2005},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2004,
  title     = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  publisher = {{IEEE}},
  year      = {2004},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255},
  isbn      = {0-7803-8251-X},
  timestamp = {Fri, 20 May 2016 09:53:46 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2004},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/icassp/2003,
  title     = {2003 {IEEE} International Conference on Acoustics, Speech, and Signal
               Processing, {ICASSP} '03, Hong Kong, April 6-10, 2003},
  publisher = {{IEEE}},
  year      = {2003},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8535},
  isbn      = {0-7803-7663-3},
  timestamp = {Fri, 02 May 2014 14:58:02 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icassp/2003},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/icecsys/2003,
  title     = {Proceedings of the 2003 10th {IEEE} International Conference on Electronics,
               Circuits and Systems, {ICECS} 2003, Sharjah, United Arab Emirates,
               December 14-17, 2003},
  publisher = {{IEEE}},
  year      = {2003},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9125},
  isbn      = {0-7803-8163-7},
  timestamp = {Tue, 24 Jun 2014 15:31:32 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/icecsys/2003},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2003,
  title     = {Proceedings of the 2003 International Symposium on Circuits and Systems,
               {ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
  publisher = {{IEEE}},
  year      = {2003},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570},
  isbn      = {0-7803-7761-3},
  timestamp = {Fri, 20 May 2016 10:01:57 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2003},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2002,
  title     = {Proceedings of the 2002 International Symposium on Circuits and Systems,
               {ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
  publisher = {{IEEE}},
  year      = {2002},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7897},
  isbn      = {0-7803-7448-7},
  timestamp = {Fri, 20 May 2016 10:09:31 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2002},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2001,
  title     = {Proceedings of the 2001 International Symposium on Circuits and Systems,
               {ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
  publisher = {{IEEE}},
  year      = {2001},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7344},
  isbn      = {0-7803-6685-9},
  timestamp = {Fri, 20 May 2016 10:15:21 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2001},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/2000,
  title     = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
               Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
               May 2000, Proceedings},
  publisher = {{IEEE}},
  year      = {2000},
  url       = {http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=18601},
  timestamp = {Sun, 22 Oct 2017 13:09:25 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/2000},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/iscas/1999,
  title     = {Proceedings of the 1999 International Symposium on Circuits and Systems,
               {ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
  publisher = {{IEEE}},
  year      = {1999},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6311},
  isbn      = {0-7803-5471-0},
  timestamp = {Fri, 20 May 2016 10:19:45 +0200},
  biburl    = {http://dblp.org/rec/bib/conf/iscas/1999},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
maintained by Schloss Dagstuhl LZI at University of Trier