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Semantic ScholarICCAD 1996: San Jose, California, USA
Rob A. Rutenbar, Ralph H. J. M. Otten:
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996. IEEE Computer Society / ACM 1996, ISBN 0-8186-7597-7- Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser:
Logic optimization by output phase assignment in dynamic logic synthesis. 2-7 - Xiaoqing Wen, Kewal K. Saluja:
A new method towards achieving global optimality in technology mapping. 9-12 - Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. 13-17 - Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar:
An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. 20-23 - Steven D. Corey, Andrew T. Yang:
Automatic netlist extraction for measurement-based characterization of off-chip interconnect. 24-29 - Andrew B. Kahng, Kei Masuko, Sudhakar Muddu:
Analytical delay models for VLSI interconnects under ramp input. 30-36 - Chung-Ping Chen, Hai Zhou, D. F. Wong:
Optimal non-uniform wire-sizing under the Elmore delay model. 38-43 - Takumi Okamoto, Jason Cong:
Buffered Steiner tree construction with wire sizing for interconnect layout optimization. 44-49 - Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs:
Identification of unsettable flip-flops for partial scan and faster ATPG. 63-66 - Elizabeth M. Rudnick, Janak H. Patel:
Simulation-based techniques for dynamic test sequence compaction. 67-73 - Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi:
Tearing based automatic abstraction for CTL model checking. 76-81 - Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose:
CTL model checking based on forward state traversal. 82-87 - Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee:
VERILAT: verification using logic augmentation and transformations. 88-95 - Youngsoo Shin, Kiyoung Choi:
Software synthesis through task decomposition by dependency analysis. 98-104 - Wei Zhao, Christos A. Papachristou:
Synthesis of reusable DSP cores based on multiple behaviors. 103-108 - Hakan Yalcin, John P. Hayes, Karem A. Sakallah:
An approximate timing analysis method for datapath circuits. 114-118 - Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer:
Static timing analysis for self resetting circuits. 119-126 - David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah:
Timing verification of sequential domino circuits. 127-132 - Gunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser:
Basic concepts for an HDL reverse engineering tool-set. 134-141 - Hsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul:
Clock-driven performance optimization in interactive behavioral synthesis. 154-157 - Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register-transfer level estimation techniques for switching activity and power consumption. 158-165 - Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah:
Optimization of custom MOS circuits by transistor sizing. 174-180 - Jason Cong, Lei He:
An efficient approach to simultaneous transistor and interconnect sizing. 181-186 - Edoardo Charbon, Paolo Miliozzi, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli:
Generalized constraint generation in the presence of non-deterministic parasitics. 187-192 - Shantanu Dutt, Wenyong Deng:
VLSI circuit partitioning by cluster-removal using iterative improvement techniques. 194-200 - Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan:
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. 201-204 - Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Compact and complete test set generation for multiple stuck-faults. 212-219 - João P. Marques Silva, Karem A. Sakallah:
GRASP - a new search algorithm for satisfiability. 220-227 - Hisashi Kondo, Kwang-Ting Cheng:
Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. 228-232 - N. P. van der Meijs, T. Smedes:
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. 244-251 - Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
A new method to express functional permissibilities for LUT based FPGAs and its applications. 254-261 - Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska:
Fast Boolean optimization by rewiring. 262-269 - Qi Wang, Sarma B. K. Vrudhula:
Multi-level logic optimization for low power using local logic transformations. 270-277 - Roland W. Freund, Peter Feldmann:
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm. 280-287 - Luís Miguel Silveira, Mattan Kamon, Ibrahim M. Elfadel, Jacob White:
A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. 288-294 - Peter Feldmann, Jaijeet S. Roychowdhury:
Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm. 295-300 - Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang:
Post global routing crosstalk risk estimation and reduction. 302-309 - Joe G. Xi, Wayne Wei-Ming Dai:
Jitter-tolerant clock routing in two-phase synchronous systems. 316-320 - Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel:
Enhancing high-level control-flow for improved testability. 322-328 - Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design for testability technique for RTL circuits using control/data flow extraction. 329-336 - Pranav Ashar, Aarti Gupta, Sharad Malik:
Using complete-1-distinguishability for FSM equivalence checking. 346-353 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Improved reachability analysis of large finite state machines. 354-360 - Hans T. Heineken, Wojciech Maly:
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. 368-373 - Eric Felt, Stefano Zanella, Carlo Guardiani, Alberto L. Sangiovanni-Vincentelli:
Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling. 374-380 - Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai:
A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects. 381-386 - Daniel Brand, Chandramouli Visweswariah:
Inaccuracies in power estimation during logic synthesis. 388-394 - Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska:
Clock skew optimization for ground bounce control. 395-399 - Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A power modeling and characterization method for the CMOS standard cell library. 400-404 - Kyosun Kim, Ramesh Karri, Miodrag Potkonjak:
Heterogeneous built-in resiliency of application specific programmable processors. 406-411 - Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer:
An observability-based code coverage metric for functional simulation. 418-425 - Ellen Sentovich, Horia Toma, Gérard Berry:
Latch optimization in circuits generated from high-level descriptions. 428-435 - Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu:
An algorithm for synthesis of system-level interface circuits. 442-447 - Chad Young, Giorgio Casinovi, Jonathan Fowler, Paul Kerstetter:
An algorithm for power estimation in switched-capacitor circuits. 450-454 - Edoardo Charbon, Ranjit Gharpurey, Alberto L. Sangiovanni-Vincentelli, Robert G. Meyer:
Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs. 455-462 - Iasson Vassiliou, Henry Chang, Alper Demir, Edoardo Charbon, Paolo Miliozzi, Alberto L. Sangiovanni-Vincentelli:
A video driver system designed using a top-down, constraint-driven methodology. 463-468 - Takayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe:
Hybrid floorplanning based on partial clustering and module restructuring. 478-483 - Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
Module placement on BSG-structure and IC layout applications. 484-491 - Mukund Sivaraman, Andrzej J. Strojwas:
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. 494-501 - Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
SIGMA: a simulator for segment delay faults. 502-508 - Minesh B. Amin, Bapiraju Vinnakota:
Zamlog: a parallel algorithm for fault simulation based on Zambezi. 509-512 - Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli:
Digital sensitivity: predicting signal interaction using functional analysis. 536-541 - Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. 547-554 - Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh:
Simulation and sensitivity analysis of transmission line circuits by the characteristics method. 556-562 - Mustafa Celik, Andreas C. Cangellaris:
A general dispersive multiconductor transmission line model for interconnect simulation in SPICE. 563-568 - Sharad Kapur, David E. Long, Jaijeet S. Roychowdhury:
Efficient time-domain simulation of frequency-dependent elements. 569-573 - Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu, Massoud Pedram:
Stratified random sampling for power estimation. 576-582 - Cheng-Ta Hsieh, Qing Wu, Chih-Shun Ding, Massoud Pedram:
Statistical sampling and regression analysis for RT-level power evaluation. 583-588 - Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting:
Metrology for analog module testing using analog testability bus. 594-599 - Balakrishnan Iyer, Maciej J. Ciesielski:
Metamorphosis: state assignment by retiming and re-encoding. 614-617 - Vigyan Singhal, Sharad Malik, Robert K. Brayton:
The case for retiming with explicit reset circuitry. 618-625 - Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk:
Polarized observability don't cares. 626-631 - Inki Hong, Miodrag Potkonjak:
Power optimization in disk-based real-time application specific systems. 634-637 - Wen-Jong Fang, Allen C.-H. Wu:
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. 638-643 - Vaughn Betz, Jonathan Rose:
Directional bias and non-uniformity in FPGA global routing architectures. 652-659 - Avaneendra Gupta, John P. Hayes:
Width minimization of two-dimensional CMOS cells using integer programming. 660-667 - Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai:
Interchangeable pin routing with application to package layout. 668-673 - Xiao-Tao Chen, Fabrizio Lombardi:
A coloring approach to the structural diagnosis of interconnects. 676-680 - Kanad Chakraborty, Pinaki Mazumder:
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. 685-688 - Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag:
Design for manufacturability in submicron domain. 690-697 - Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy:
Embedded tutorial: Speed - new paradigms in design for performance. 700
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