BibTeX record conf/asap/SenanayakeLWAAT17

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@inproceedings{DBLP:conf/asap/SenanayakeLWAAT17,
  author    = {Rishan Senanayake and
               Namitha Liyanage and
               Sasindu Wijeratne and
               Sachille Atapattu and
               Kasun Athukorala and
               P. M. K. Tharaka and
               Geethan Karunaratne and
               R. M. A. U. Senarath and
               Ishantha Perera and
               Ashen Ekanayake and
               Ajith Pasqual},
  title     = {High performance hardware architectures for Intra Block Copy and Palette
               Coding for {HEVC} screen content coding extension},
  booktitle = {28th {IEEE} International Conference on Application-specific Systems,
               Architectures and Processors, {ASAP} 2017, Seattle, WA, USA, July
               10-12, 2017},
  pages     = {164--169},
  year      = {2017},
  crossref  = {DBLP:conf/asap/2017},
  url       = {https://doi.org/10.1109/ASAP.2017.7995274},
  doi       = {10.1109/ASAP.2017.7995274},
  timestamp = {Mon, 19 Feb 2018 16:01:50 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/asap/SenanayakeLWAAT17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asap/2017,
  title     = {28th {IEEE} International Conference on Application-specific Systems,
               Architectures and Processors, {ASAP} 2017, Seattle, WA, USA, July
               10-12, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7990450},
  isbn      = {978-1-5090-4825-0},
  timestamp = {Fri, 04 Aug 2017 13:48:36 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asap/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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